This simulates Tomasulo's algorithm for a floating-point MIPS-like instruction pipeline, demonstrating out-of-order execution. The source is on GitHub.
Click instructions on the right to issue and execute them. Instructions will only execute if all of their data dependencies have been resolved, but they may issue in any order (though at least issuing them in order is recommended). Currently, loads have two-step execution and still require a writeback cycle. Regs[x] is the value at location x from the register file.
Color codes are as follows: destination source occupied source occupied destination.